EDN

Static FPGA’s Can Take Advantage of Dynamic Reconfiguration

Instant on and ready to go can be a selling point when choosing an FPGA. A part that powers up ready to roll has some advantages over statically configured FPGA's that need to be loaded and ...
Design-Reuse

Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs

Henderson, NV – February 6, 2023 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated its popular linting tool ALINT-PRO ...
EDN

Power-aware FPGA design (Part 1)

Power consumption requirements in new autonomous, multimedia-savvy consumer products that can store, transmit, and receive data have catapulted system architects and board and chip designers into a ...
Electronic Design

FPGA Tool Suite Adds Native Static Timing Analysis

With so many ASIC designers moving over to FPGAs for implementation, FPGA tool flows are looking more and more like ASIC flows. Case in point: Actel's Libero IDE 6.2 adds native static timing analysis ...
Semiconductor Engineering

Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO

Aldec’s ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers ...
Design-Reuse

Synopsys steps up efforts in FPGA design tools

Synopsys steps up efforts in FPGA design tools By Michael Santarini, EE Times September 11, 2001 (2:21 p.m. EST) URL: http://www.eetimes.com/story/OEG20010911S0037 ...
Electronics Weekly

Low power FPGA design: is it process or architecture?

Power consumption is becoming an increasingly important variable when it comes to calculating a carbon footprint for tele­com infrastructure projects. For example, on average, each fully loaded 3G ...
Electronic Design

Innovate for Low Power in A High-Performance FPGA

Traditionally, digital logic has not consumed significant static power, but this has changed dramatically as process nodes shrink. Leakage current in digital logic is now the primary challenge for ...
Electronics Weekly

FPGA promises to cut static power

Samples are now available of the first device in Xilinx’s latest FPGA family, Virtex 4, while further technical details have been released. The Virtex 4 family comes in three sub-families, ...
New Electronics

Aldec releases Static Linting and CDC Analysis for Microchip FPGA and SoC designs

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has announced that it has updated its linting tool ALINT-PRO to enhance the support ...
Financial Post

Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs

Static linting helps detect a wide variety of design issues, including poor coding styles, improper clock and reset management, simulation vs. synthesis mismatches, incorrectly implemented finite ...